Décharge électrostatique en électronique

This cluster of papers focuses on the design, analysis, and modeling of electrostatic discharge (ESD) protection in integrated circuits, particularly in CMOS technology. It covers topics such as SCR devices, LDMOS design, RF ESD protection, TLP calibration, high-voltage ESD solutions, and latchup immunity. The papers also discuss on-chip protection strategies and system-level ESD testing.